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* chinese/ports/index.wml uptodatevifly2020-03-261-3/+3
* chinese/ports/index.wml uptodatevifly2020-01-251-10/+12
* replaced AVR32 link with archive linkarchitW2020-01-021-1/+1
* replaced or1k link with archive linkarchitW2020-01-021-1/+1
* Updated riscv.org link to httpsarchitW2020-01-021-1/+1
* chinese: ports/: Update explanation of "userland"Boyuan Yang2019-09-101-2/+2
* Update translations: update link to OpenRISC websitePaul Wise2019-08-131-2/+2
* (zh) update ports/index.wml to include RISC-V.Wenbin Lv2019-06-251-5/+11
* Sync translations (smart_change.pl)Guillem Jover2019-04-011-1/+1
* Sync with EnglishLaura Arjona Reina2019-03-181-16/+0
* chinese: ports/: Update to latest translationBoyuan Yang2018-11-231-2/+9
* Fix up incorrect git commit hash referenceSteve McIntyre2018-06-071-1/+1
* chinese: Update index page and ports/amd64 pageBoyuan Yang2018-06-021-5/+5
* Switch from CVS revisions to git commit hashes in translation-check headers (...Laura Arjona Reina2018-05-313-3/+3
* Switch from http to https for links to anonscm.debian.orgPaul Wise2018-02-201-2/+2
* update chinese translationsFl Yang2017-09-134-0/+101
* change to small MakefileFl Yang2017-08-091-13/+1
* update for EnglishFl Yang2017-08-072-0/+362

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