From f7168201de54cbd3ed936908eb49068052dedbbe Mon Sep 17 00:00:00 2001 From: Salvatore Bonaccorso Date: Wed, 10 Jun 2020 12:15:24 +0200 Subject: Expand planned text for intel-microcode update --- dsa-texts/intel-microcode.20200609 | 3 +++ 1 file changed, 3 insertions(+) diff --git a/dsa-texts/intel-microcode.20200609 b/dsa-texts/intel-microcode.20200609 index 0c6129f6..40e46bd0 100644 --- a/dsa-texts/intel-microcode.20200609 +++ b/dsa-texts/intel-microcode.20200609 @@ -6,6 +6,9 @@ provides mitigations for the Special Register Buffer Data Sampling (CVE-2020-0543), Vector Register Sampling (CVE-2020-0548) and L1D Eviction Sampling (CVE-2020-0549) hardware vulnerabilities. +The microcode update for HEDT and Xeon CPUs with signature 0x50654 which +was reverted in DSA 4565-2 is now included again with a fixed release. + For details refer to https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00320.html https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00329.html -- cgit v1.2.3